1. Field of the Invention
The present invention relates to a technique of estimating a simultaneous switching noise (SSN) (also referred to as simultaneous switching output (SSO) noise) caused by simultaneous switching of signals input into and output from a plurality of pins in a semiconductor device.
2. Description of the Related Art
An FPGA (Field Programmable Gate Array) is a semiconductor device that allows a user to set any pin arrangement, circuit configuration, and the like.
With an increase in the number of IO pins and the operation speed of circuits in the FPGA, simultaneous switching noise that is caused by the simultaneous switching of signals output from a large number of output pins can no longer be neglected.
Conventionally, ground bouncing occurring between reference levels of a ground pin in a device package and the ground of an internal die in the device has been one of the main causes of erroneous switching in high-speed devices. The erroneous switching can be caused by only one signal line; thus, when there is a plurality of lines for signals that switch simultaneously, any noise that they can cause is a serious problem.
Therefore, in a board including an FPGA, it is necessary to estimate the level of simultaneous switching noise on the basis of the pin arrangement of the FPGA via a simulation during a design phase in order to cause the FPGA device to operate appropriately.
In the case when a simulator such as, for example, a SPICE or the like is used, the simultaneous switching noise can be estimated relatively accurately. However, this method of simulation takes a long time.
Japanese Patent Application Publication No. 2000-285146 (referred to as Patent Document 1 hereinafter) discloses a technique of suppressing noise caused in branch power source lines. In this technique, a plurality of logic cells connected to one branch power source line are categorized into one arrangement of a logic cell group, the value of simultaneous switching noise that is expected to be caused by the simultaneous switching of a plurality of logic cell groups is obtained on the basis of a noise value for each arrangement of a logic cell, and the delay time of a plurality of delay adjustment buffers inserted into the logic cell group is adjusted on the basis of the comparison result between the total value of noise limitation value of the plurality of logic cell groups constituting the logic cell group arrangement and the expected simultaneous switching noise value.